The present invention relates to a semiconductor integrated circuit device. More specifically, the invention relates to a technology particularly effective in application for ASIC (Application Specific Integrated Circuit or Application Specific Standard Product) device.
Designing theory of ASIC device covers all of semiconductor integrated circuit devices employing any of standard cell type, gate array type, custom type and so forth. ASIC devices are generally designed and developed in the aid of a design automation system (DA: Design Automation) typically using a computer. For example, in the case of the semiconductor integrated circuit device employing the standard cell system, it is typical process to store a plurality of macro-cells (functional circuit blocks) which are preliminarily designed with optimal designs, to arrange some macro-cells depending upon necessity, and to mutually connect these macro-cells. Accordingly, the semiconductor integrated circuit devices employing the standard cell system is featured in short turn around time and relatively high density and circuit performance, and thus is suitable for production in wide variety and small production amount.
The ASIC device is generally formed with a rectangular monocrystalline silicon substrate. In the central area on the main surface of the monocrystalline silicon substrate (semiconductor substrate), an internal logic circuit including a plurality of and a plural kinds of macro-cells is formed. On the peripheral portion of the internal logic circuit formed on the main surface of the monocrystalline silicon substrate, an input/output circuit including either of or both of an input circuit and an output circuit is formed. On the peripheral portion of the input/output circuit on the main surface of the substrate, a plurality of external terminals (bonding pads) are further arranged.
One or more ASIC devices, each of which is to be assembled in a large scale computer and thus required high arithmetic processing speed and high density, are mounted on a mounting board, such as mother board, testing board or so forth, utilizing face-down bonding. In the face-down bonding, soldering bump electrodes are interposed between external terminals of the ASIC device and terminals of the mounting board for mechanically and electrically connecting therebetween.
In the face-down bonding signal propagation paths and power supply paths between the external terminals of the ASIC device and the terminals of the mounting board are shorter than in the wire bonding. Namely, shortening of the signal propagation paths is expected to achieve higher signal propagation speed and thus to contribute to a higher speed circuit operation. On the other hand, shortening of the power supply paths is expected to achieve suppression of power source noise and to contribute to stability of the circuit operation. Therefore, improvement of the circuit operation speed of the ASIC device can be expected.
Also, the face-down bonding permits reduction of an occupation area and a high density since, when a plurality of ASIC devices are mounted on a single mounting board, a part of an encapsulating material for the ASIC device can be used in common by a plurality of the ASIC devices (known as a multi-chip module).
Furthermore, the face-down bonding permits forced cooling from the reverse side (other main surface of the monocrystalline silicon substrate, where no circuit is mounted). Namely, in the case of the ASIC device causing large heat generation, such as the ASIC device, in which the internal logic circuit is constituted principally with bipolar transistors, reliability of the circuit operation will certainly be assured.
JP-A-62-194640 (laid-open on Aug. 27, 1987) shows a semiconductor integrated circuit device employing bump-mounting technique, in which a number of bumps are arranged to be distributed all over the surface of a semiconductor chip, I/O gate cells in a gate array are arranged along the periphery of the chip and in boundary areas on the chip surface which divide the chip surface into regions, and internal gates are arranged in the regions.